期末上機考(完成)

module top;

wire a, b, c, d, f;
system_clock #400 clock1(a);
system_clock #200 clock2(b);
system_clock #100 clock2(c);
system_clock #50  clock2(d);

not a1(A,a);
not b1(B,b);
not c1(C,c);
not d1(D,d);
and f1(F1,A,B,c);
and f2(F2,A,c,D);
and f3(F3,b,C,d);
and f4(F4,a,b,d);
and f5(F5,a,B,C,D);
and f6(F6,a,B,c,D);
or  f (F,F1,F2,F3,F4,F5,F6);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule